Zen DDR4 support.

[duby229]

http://www.extremetech.com/extreme/198386-amds-next-gen-cpu-leak-14nm-simultaneous-multithreading-and-ddr4-support

OK, so the biggest problem compute platforms face is memory bandwidth.

And DDR4 is still only 64 f-ing bits. That's 4 dimms needed to max out Zens memory controller. In my personal opinion it's ok for mobile dimms to be 64bits, but not for desktop. If a 128bit buss is too hard to etch then it's time to move on to a serial buss. JEDEC has seriously been holding memory technologies back. Not so so much as far as IC technology goes, but very much so in the memory interface technology.

Let's face it, JEDEC is a standards providing body. It's their job to make standards, and they suck at their job.

Though, HBM sounds nice. I can't wait to see it on an APU. I just really hope AMD completely redesigned the internal northbridge.

[bridgman]

If a 128bit buss is too hard to etch then it's time to move on to a serial buss. JEDEC has seriously been holding memory technologies back. Not so so much as far as IC technology goes, but very much so in the memory interface technology.

There are limits to what you can do with faster serial links, since the wide links we have today run at over a gigahertz. Board wiring from CPU to memory is already a fairly black art, and there's a point where it's not really practical to run a bus that fast over a PCB.

Let's face it, JEDEC is a standards providing body. It's their job to make standards, and they suck at their job.

It's JEDEC's job to manage standards, not to make new ones. HBM was driven by AMD and Hynix before becoming a JEDEC standard, for example.