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First Linux Benchmarks Of AMD FX-8150 Bulldozer

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  • #31
    Is this a new forum gimmick? Deanjo's golden stars?

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    • #32
      Originally posted by pingufunkybeat View Post
      Is this a new forum gimmick? Deanjo's golden stars?
      Did you want one too? lol

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      • #33
        Originally posted by deanjo View Post
        Well even with Integer and Floating point calculations you can still get even better performance with fine tuned hand written optimizations. But I will still give you a gold star. ;D

        they thank you and i know this: "Well even with Integer and Floating point calculations you can still get even better performance with fine tuned hand written optimizations. "

        i just want to write some basic stuff about compilers.
        the people are so brain-death they think the compiler fix all there problem magic magic...

        the difference between compiler in Integer+Floating vs hand written Assembler is not so big than Compiler vs SIMD units....

        SIMD instructions set blow the compiler away...

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        • #34
          Originally posted by nepwk View Post
          I disagree. Intel regularly uses it's monopoly to force it's technology on everybody, and the constant influx of SSE instructions are what keep the x86 monopoly going. AMD could come up with their own instructions, but how well do you think they would do with incompatible instructions and significantly less marketshare? Furthermore, there's only so many instructions that are actually useful, Intel could sue them for IP infringement if anything was deemed to similar.
          If the new instructions were actually useful, they would get used. See Via Padlock, being supported in nearly every relevant sw (you can even mine bitcoins on it, as fast as on an Intel quad ).

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          • #35
            Originally posted by nepwk View Post
            If AMD were to start doing their own thing with instructions, then AMD's x86 would quickly turn into a fringe server architecture that only runs operating systems specially compiled for it with GCC, like any other number of CPUs from IBM, Sun, etc... So following Intel's lead is still their best option, and things won't change until regulators grow a pair and decide to break up the Intel monopoly racket.
            Can't say I agree there since quite the opposite happened when AMD did introduce x86-64 extensions which where quite different then anything intel was offering at the time.

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            • #36
              Originally posted by mcirsta View Post
              You say it needs improvements in the kernel, well who exactly stopped AMD from pushing this 1 year ago when they had their first Bulldozer samples ready, could test and all of that. That's how you do things, not wait till it's out, then say, oh but it will work better with these.
              Fear of giving away too much info too early? Last minute die changes? I'm actually curious.
              I do think BD has had a fairly catastrophic release, though people paint all black way too fast.

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              • #37
                Originally posted by Qaridarium View Post
                they thank you and i know this: "Well even with Integer and Floating point calculations you can still get even better performance with fine tuned hand written optimizations. "

                i just want to write some basic stuff about compilers.
                the people are so brain-death they think the compiler fix all there problem magic magic...

                the difference between compiler in Integer+Floating vs hand written Assembler is not so big than Compiler vs SIMD units....

                SIMD instructions set blow the compiler away...
                But what well optimized compilers do nowadays is kind of magic.
                I remember running a knapsack programming assignment written in ADA and compiled with gcc-ada on some server with Opteron 275 and on my netbook with an Atom N270. The server had Ubuntu with gcc 4.4 and my netbook Archlinux with gcc 4.5 I believe. The netbook ran it faster...

                Now I'm a bit tired and I'm not very deep into compilers, but can compilers really not "abuse" those instructions and for example everytime the program needs to execute something like a=b*c+d (how often that may happens) run it via the FMA instruction?

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                • #38
                  Originally posted by deanjo View Post
                  Can't say I agree there since quite the opposite happened when AMD did introduce x86-64 extensions which where quite different then anything intel was offering at the time.
                  x64 isn't really the same thing as SSE/AVX/FMA, etc... x64 has more to do with memory management than anything else, the other instructions are mostly aimed at improving instruction-per-clock.

                  Besides, that's pretty much the only time they've ever won an instruction set battle. They've also created 3Dnow!, SSE4a, SSE5(or whatever it became), etc... and they never get much traction. 64-bit x86 was inevitable, AMD just beat Intel to the punch. With anything other normal instruction set that isn't destined to happen, they're going to have a hard time getting traction within the ecosystem, considering their market share.

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                  • #39
                    Originally posted by nepwk View Post
                    Besides, that's pretty much the only time they've ever won an instruction set battle. They've also created 3Dnow!, SSE4a, SSE5(or whatever it became),
                    SSE5 is what you see in BD right now, they just made it compatible with AVX and dropped the SSE5 name.

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                    • #40
                      Originally posted by deanjo View Post
                      SSE5 is what you see in BD right now, they just made it compatible with AVX and dropped the SSE5 name.
                      no SSE5 is FMA3... and they don't have FMA3 in the bulldozer they ad FMA4 because intel cheat to amd

                      now intel makes FMA3 first and amd had to ad FMA3 in the next bulldozer.

                      also the XOP is SSE5 and intel do not support it at all.

                      intel will bring FMA3 in 2013...

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                      • #41
                        Originally posted by Qaridarium View Post
                        no SSE5 is FMA3... and they don't have FMA3 in the bulldozer they ad FMA4 because intel cheat to amd

                        now intel makes FMA3 first and amd had to ad FMA3 in the next bulldozer.

                        also the XOP is SSE5 and intel do not support it at all.

                        intel will bring FMA3 in 2013...
                        SSE5 according to AMD's documents is FMA4, XOP and CVT16 as of the 2009 revision of it.

                        http://developer.amd.com/archive/cpu...s/default.aspx

                        linked document

                        http://support.amd.com/us/Embedded_TechDocs/43479.pdf

                        Comment


                        • #42
                          Originally posted by Qaridarium View Post
                          no SSE5 is FMA3... and they don't have FMA3 in the bulldozer they ad FMA4 because intel cheat to amd

                          now intel makes FMA3 first and amd had to ad FMA3 in the next bulldozer.

                          also the XOP is SSE5 and intel do not support it at all.

                          intel will bring FMA3 in 2013...
                          Nope wrong again... XOP AND FMA4 were parts SSE5 that were not compatible with AVX and so they were spun off into their own extensions. The rest of SSE5 was compatible with AVX and so thats what it became.

                          EDIT: FMA3 is not the same as FMA4

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                          • #43
                            Originally posted by duby229 View Post
                            Nope wrong again... XOP AND FMA4 were parts SSE5 that were not compatible with AVX and so they were spun off into their own extensions. The rest of SSE5 was compatible with AVX and so thats what it became.

                            EDIT: FMA3 is not the same as FMA4
                            Exactly...

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                            • #44
                              Originally posted by deanjo View Post
                              SSE5 according to AMD's documents is FMA4, XOP and CVT16 as of the 2009 revision of it.

                              http://developer.amd.com/archive/cpu...s/default.aspx

                              linked document

                              http://support.amd.com/us/Embedded_TechDocs/43479.pdf
                              as i know amd come with SSE5 first this means (FMA3+XOP+CVT16)

                              then intel comes with the name AVX and the claim that FMA4 is better than FMA3 and they claim that they will not support FMA3.

                              then AMD chance the logic to AVX and FMA4 then intel cheat on amd and intel go for AVX first and in 2013 AVX+FMA3

                              now amd do have only 01 bin compatibility on SSE4.2 the bulldozer is not compatible with AVX and not compatible with FMA4.

                              in 2013 intel will bring the AVX+FMA3 and amd have to ad this to...

                              then in 2015 intel ad FMA4 and then in 2017 they will allow amd to make there cpus bit compatible in AVX+FMA3+FMA4

                              and no right now amd claim to support AVX and FMA4 but they can not because intel do not allow it!

                              its a AVX-AMD-only-slang and FMA4-AMD-only-slang

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                              • #45
                                Originally posted by duby229 View Post
                                EDIT: FMA3 is not the same as FMA4
                                right FMA3 is a complete different feature.

                                first amd came with FMA3 then intel claim they will not support FMA3 they will only support AMA4 then amd chance there amd-only instruction set to FMA4 after that intel chance there plan to support only FMA3.

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