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AMD Reverse HT on Linux

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  • AMD Reverse HT on Linux

    For a while now there have been rumors surfacing around the Internet of Advanced Micro Devices (AMD) developing a reverse Hyper-Threading technology. This technology would basically be an inverse of Intel's Hyper-Threading to make two cores function as one. It was believed by some that the technology was already embedded into the Athlon 64 X2 AM2 processors, and that shortly after Intel releases Conroe, AMD would come to the table with a miracle BIOS update and driver to implement this function. The purpose of reverse Hyper-Threading would be to improve the performance in single-threaded environments.

    What has yet to be cleared from Phoronix sources is the position of Reverse HT on Linux, and if there would be such support. On top of an updated motherboard BIOS, it is expected that a new driver will be needed. Microsoft has been reportedly developing a Windows patch/update so the two physical AMD cores are properly recognized as a single core. Though, with much in Linux already supporting SMP, it's unclear as to the extent of the benefits in most environments, and if the support would even be available. Though, if any unprotected words come along about Reverse HT + Linux, it will be passed along.

    Contrary to the reports of AM2 Reverse HT coming along shortly after the Conroe launch, a very reliable source has reported to us that this technology won't actually appear until becoming a feature with the K10/K8L Greyhound generation...

    Just some food for thought, and of course, Advanced Micro Devices has not officially commented on these matters.

    Feel free to discuss Reverse Hyper-Threading/Anti Hyper-Threading.
    Michael Larabel
    http://www.michaellarabel.com/

  • #2
    Does anyone know if this feature would negate the benefits of having SMP for multitasking?

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    • #3
      Originally posted by James
      Does anyone know if this feature would negate the benefits of having SMP for multitasking?
      SMP basically implies multiple (virtual in the case of HT) CPUs. Reverse HT would mean that you'd still get to use both or more cores for multitasking, but running a single process would use them, too, since the cores would then "cooperate".

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      • #4
        Originally posted by James
        Does anyone know if this feature would negate the benefits of having SMP for multitasking?
        That's what I'm afraid of, some resource hungry app *cough*Firefox*cough*all of Gnome*cough* eating all your resources. That's what's made SMP so lucrative to enthusiasts for years, the second core can just handle other process' when something tries to run off and sit in a corner hoarding all your CPU time like a greedy toddler. I hope Linux either allows you to disable reverse HT altogether, or revamps nice levels, allowing you to squeeze in additional process' on a second CPU more easily if a process is already bogarting the first CPU.

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        • #5
          I highly doubt this reverse HT will work, I guess it's more a rumor than news.

          Reverse HT had to rewrite the code so that multiple threads can run at the same time. Expressed differently the single threaded program has to be rewritten multi threaded. This is hard for programmers who are intelligent compared to a CPU. Compilers can do it to some extend, but how is a CPU supposed to do this in hardware and in realtime ? I don't think we'll ever see this.

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          • #6
            My sources that I have spoken with on this matter are still stating that we will see Reverse HT (/Anti-HT) with K10/K8L Greyhound parts.
            Michael Larabel
            http://www.michaellarabel.com/

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            • #7
              Originally posted by Michael View Post
              My sources that I have spoken with on this matter are still stating that we will see Reverse HT (/Anti-HT) with K10/K8L Greyhound parts.
              I'd be pleasantly surprised if it works, but I still doubt it. Maybe someone can enlighten me how this should work. How can a CPU execute a single thread on multiple CPUs cores ? How can Core #2 execute an instruction that depends on the result of the previouse one still running on Core #1 ?

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              • #8
                I would be 100% certain it doesn't magically rewrite the code correctly. My guess is it would use the second core to become a co-processor. When possible it would execute instructions ahead of time so the main processor doesn't need to do them. So obviously you wouldn't see a huge performance improvement but it would help .

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                • #9
                  Originally posted by siti View Post
                  When possible it would execute instructions ahead of time so the main processor doesn't need to do them. So obviously you wouldn't see a huge performance improvement but it would help .
                  How can the second processor execute something ahead in time. Usually the instructions "ahead in time" depend on the instructions which are being executed. The question then is the same: How does the CPU know, which instructions depend on each other and which not. In other words: Which instructions can be parallelized. In yet other words: Which instructions can be put into different threads ? You end up again with multiple threads, even if those are "micro"-threads which are just some very few instructions.

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                  • #10
                    Pure speculation, but with some sort of multi-cpu register coherency mechanism it should be possible to pipeline execution across multiple processors in manner similar to a single cpu.

                    I don't know if that is feasible though...

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                    • #11
                      Originally posted by James View Post
                      Pure speculation, but with some sort of multi-cpu register coherency mechanism it should be possible to pipeline execution across multiple processors in manner similar to a single cpu.
                      Having more than one CPU core executing a single instruction stream would give new dimensions to speculative execution. Good branch prediction is one thing, having multiple cores simply go ahead and speculatively execute both outcomes of the branch could boost the IPC.

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                      • #12
                        This has been done before. The very first IBM POWER cpu was actually a full card with 7 chips I think. One was an instruction dispatcher, and the others were execution units for floating point/integer operations. Each time an instruction arrived to the cpu, it would be sent by the dispatcher to an available core. The dispatcher would also store the results back in memory.

                        I have such a beast , it says 1991 on it (FWIW, it's an IBM powerserver 320).

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                        • #13
                          Originally posted by marcheu View Post
                          This has been done before. The very first IBM POWER cpu was actually a full card with 7 chips I think. One was an instruction dispatcher, and the others were execution units for floating point/integer operations. Each time an instruction arrived to the cpu, it would be sent by the dispatcher to an available core. The dispatcher would also store the results back in memory.

                          I have such a beast , it says 1991 on it (FWIW, it's an IBM powerserver 320).
                          IBM has done alot of things before... but the situation (or problem if you tend to like IBM and what it does) is that other people come along and do it at the right time, in a different way, or with the right marketing and make a ton of money off of it. Take for instance Windows versus OS/2. Obviously OS/2 was around before Windows, and many people say it was more technologically advanced. But Windows came out and was marketed in a way that made it sell much better than OS/2. You could say the same thing about Power architecture in general (versus x86-based processors).

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